Contemporary computer systems often implement hierarchical caching structures in which multiple levels of data cache are utilized to maximize the data processing performance of the complete system. Similarly, contemporary computers routinely use multiple processors, each having multiple levels of data cache, connected through a system bus to a main memory as well as various input/output devices or buses. In the context of such systems, the cache read and write operations are commonly performed through burst mode data transfer cycles. Burst mode transfers are used because they maximize the utilization of the bus bandwidth, in recognition of the fact that bus contention, especially in multiprocessor systems, is proving to be a major constraint on the throughput of the complete system.
The number of data transfer cycles in a burst, often referred to as beats, is equal to the cache line size divided by the width of the data bus. The units of measure are routinely, but not necessarily, bytes, identified within the drawings by the designator "B". The writing of modified data from cache back to main memory is normally accomplished in a burst mode encompassing the full cache line, as implemented through cache controller. This convention of transferring the full cache line occurs even if only one byte of the data in the cache line was actually altered as an aspect of processor activity prior to the writeback cycle. The initiation of the writeback cycle is attributable to a number of causes, examples including normal cache deallocation (cast out), a cross deallocation due to a snoop hit (multiprocessor systems), or due to a deliberate cache management instruction being executed by the processor.
The conventional practice of writing back the full cache line, even if done in a burst mode, consumes multiple clock cycles, at least equal in number to the beats of the burst to transfer the complete cache line. Yet, in multiprocessor and faster uniprocessor systems bus contention is becoming a major limitation on computer system performance. Thus, what is needed is a system and method by which cache writeback can be accomplished in a burst mode adaptable at the granularity of the data bus to transfer only modified data from the cache to main memory.